Three-dimensional (3D) packaging is short for 3D die stacking using through-silicon vias (TSVs), conceptually similar to nails, as opposed to wire-bonds for connecting the dies to the package substrate. A 3D integrated circuit (3DIC) may contain two or more dies (layers), each of which could include a partial or full system-on-chip (SOC) logic that may contain tens to hundreds of millions of gates.
In a typical 3D chip, I/O pads are not available to all dies (layers). Instead, they are only bonded to the bottom layer, and functional signal values must be elevated from the bottom layer to upper layers via TSVs (also referred to as functional TSVs).
Due to increased SOC complexity and gate count, test data volume and test application time (that affect test cost) have increased dramatically even for single stuck-at faults. With the widespread use of deep submicron (DSM) processes, the need for low power test patterns to detect path-delay faults, transition faults, and bridging faults is becoming greater to maintain the quality and avoid yield loss of next-generation SOC manufacturing. Such requirement further drives up test cost.
One prior art widely practiced in the industry today to reduce test cost while ensuring that the total number of external scan chains (often referred to as scan channels) stays within the I/O pad count limit of the chip package during manufacturing test is scan compression [1-4]. The conventional scan compression architecture is shown in FIG. 1. It has been shown that scan compression can provide 10 to 100 times (10× to 100×) reduction in test data volume and test application time and hence can drastically reduce manufacturing test cost. The approach usually assumes a 1-to-n scan configuration, in which the number of internal scan chains is n times that of external scan inputs/outputs (referred to as scan I/O pads). A decompressor is added before internal scan chains for stimulus decompression and a compactor is added after internal scan chains for response compaction (see FIG. 1).
A second prior art is to employ a bandwidth matching or time-division demultiplexing/multiplexing (TDDM/TDM) technique proposed in [5-7] to further reduce test cost for SOC testing. The general bandwidth-matching architecture is shown in FIG. 2. Because typical I/O pads of a chip are designed to operate at very high frequencies, the idea is to take advantage of the high-speed I/O's of a chip, ranging from a few hundred MHz to a few GHz. By contrast, internal scan chains usually only operate at a much lower frequency, ranging from 10 MHz to 100 MHz. By shifting in and out scan data at a high data rate on the scan inputs through a TDDM/TDM or bandwidth-matching circuit, test application time can be further reduced by additional 10× to 100× depending on the high-speed scan I/O pads' frequency, while test data volume remains the same.
A third prior art is to use the UltraScan architecture proposed in [U.S. Pat. No. 7,512,851] that embeds a scan compression circuit in a bandwidth-matching circuit. The general UltraScan architecture is shown in FIG. 3. As the UltraScan architecture combines both scan compression and bandwidth-matching circuits, it can reduce test application time by as much as 1000× and test data volume by as much as 100×, simultaneously.
While these combined prior art solutions are effective in reducing test data volume and test application time, they are mainly used for SOC applications on a single die. Since one single 3D chip can contain two or more dies, 3DIC designers are now facing an unprecedented challenge of managing both test cost and I/O pad count limit during pre-bond and post-bond testing. Test cost is dictated by test application time and test data volume, whereas I/O pads are limited not only by the available number of pads presents on the bottom die but also by the need to route those bottom pads via TSVs to provide access to signals on other (upper) dies. Because I/O pins on upper dies cannot be accessed directly without going through the I/O pads on the bottom layer, to cope with the I/O pad count limit, one common approach is to add a multiplexer network before and after the scan chains on each die or to combine a few shorter scan chains into a single long chain so one can test with the limited pads from the bottom die to test all dies via TSVs in series. This approach increases test cost drastically. Yet another common approach is to use a smaller number of scan channels built-in on each die. This approach when combined with scan compression, unfortunately, may cause fault coverage loss as aliasing may occur more often in the SOC design.
As I/O pads in a 3DIC are usually not available to all dies (layers), which is a severe constraint, it has been reported in [8] that it would require 2n test sessions to completely test a 3DIC during pre-bond testing and post-bond testing, when the 3DIC contains n dies. During pre-bond testing, n test sessions are required to test all bare dies one at a time. During post-bond testing, n−1 test sessions are required to test stacked dies 1 and 2 first, 1, 2, and 3 next, etc., where die 1 is the bottom die that connects to the I/O pads. A final test is for the whole packaged chip. This may pose a serious problem as a 2n test cost is economically infeasible. How to fully utilize scan technology in a 3DIC yet still to reduce test cost and improve fault coverage is now becoming a very important challenge.
Therefore, there is a need to further reduce test cost as well as reduce the number of test sessions for both pre-bond and post-bond testing. There is also a need to ensure that the total number of external scan chains stays within the I/O pad count limit of the chip packaging during pre-bond and post-bond testing. In addition, due to the severe constraint on I/O pads which are only available on the bottom layer, there is further a need for a 3DIC design methodology to comply with a set of 3D scan design rules so as to fully utilize scan technology in the 3DIC to reap the benefit of reduced test cost and high fault coverage.